A Novel Approach to Achieve High Speed Low-power Hybrid Flip-flop
نویسندگان
چکیده
Dual dynamic hybrid flip-flop (DDFF) and a embedded logic module (DDFF-ELM) design will eliminate the large capacitance present in precharge node in various dynamic circuits. A split dynamic node structure is used to drive the output pull-up and pull-down transistor. An area, power, speed method is used to incorporate complex logic functions into the flip flop. A comparison is made in a 90 nm UMC which shows a power reduction of 27% with no speed degradation compared to the conventional flip flops. The proposed system also compares the leakage power and process-voltage-temperature of various design. A 4-b synchronous counter and 4–b Johnson up-down-counter is used to compare the DDFF and DDFF-ELM system with the other designs. The latching overhead and the less power dissipation in the proposed system indicates it is best suited for the high end technologies.
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